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SystemVerilog-2012 Only. Main part of statement parsing.
(vl-parse-statement-2012-aux atts &key (tokstream 'tokstream)
(config 'config))
→
(mv errmsg? value new-tokstream)Here's the SystemVerilog-2012 statement rule:
statement ::= [ block_identifier : ] { attribute_instance } statement_item
;;; starts with:
statement_item ::= blocking_assignment ; ;;; <complicated>
| nonblocking_assignment ; ;;; <complicated>
| procedural_continuous_assignment ; ;;; 'assign', 'deassign', 'force', 'release'
| case_statement ;;; 'case', 'casez', 'casex', 'unique', 'unique0', 'priority'
| conditional_statement ;;; 'if', 'unique', 'unique0', 'priority'
| inc_or_dec_expression ; ;;; <complicated>
| subroutine_call_statement ;;; <complicated>
| disable_statement ;;; 'disable'
| event_trigger ;;; '->', '->>'
| loop_statement ;;; 'forever', 'repeat', 'while', 'for', 'do', 'foreach'
| jump_statement ;;; 'return', 'break', 'continue'
| par_block ;;; 'fork', 'join', 'join_any', 'join_none'
| procedural_timing_control_statement ;;; '#', '@', '##'
| seq_block ;;; 'begin'
| wait_statement ;;; 'wait', 'wait_order'
| procedural_assertion_statement ;;; 'assert', 'assume', 'cover', 'restrict'
| clocking_drive ; ;;; <complicated>
| randsequence_statement ;;; 'randsequence'
| randcase_statement ;;; 'randcase'
| expect_property_statement ;;; 'expect'
Here we assume we have already parsed the block identifier and
attributes, and we just want to parse the