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          • 5.50 Uncategorized "Instructions"
          • 5.15 Fused-Multiply-Add (FMA)
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          • 5.1 General-Purpose Instructions
          • 5.10 Intel(R) SSE4.1 Instructions
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          • 5.2 X87 FPU Instructions
            • 5.2.2 X87 FPU Basic Arithmetic Instructions
            • 5.2.1 X87 FPU Data Transfer Instructions
            • 5.2.6 X87 FPU Control Instructions
            • 5.2.3 X87 FPU Comparison Instructions
            • 5.2.4 X87 FPU Transcendental Instructions
            • 5.2.5 X87 FPU Load Constants Instructions
            • 5.24 Intel(R) Memory Protection Extensions
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            • 5.14 16-Bit Floating-Point Conversion
            • 5.18 Intel(R) SHA Extensions
            • 5.11 Intel(R) SSE4.2 Instruction Set
            • 5.3 X87 FPU and SIMD State Management Instructions
            • 5.40 Other ISA Extensions
            • 5.25 Intel(R) Software Guard Extensions
            • 5.27 Control Transfer Terminating Instructions
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            • 5.30 Enqueue Store Instructions
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            • 5.26 Shadow Stack Management Instructions
            • 5.31 Intel(R) Advanced Vector Extensions 10 Version 1 Instructions
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    • 5.2 X87 FPU Instructions

    5.2.5 X87 FPU Load Constants Instructions

    Unimplemented Instructions

    Opcode Mnemonic Other Information Semantic Function
    D9 FLD1
    :REG 5
    :MOD 3
    :R/M 0
    :FEAT :FPU
    D9 FLDL2T
    :REG 5
    :MOD 3
    :R/M 1
    :FEAT :FPU
    D9 FLDL2E
    :REG 5
    :MOD 3
    :R/M 2
    :FEAT :FPU
    D9 FLDPI
    :REG 5
    :MOD 3
    :R/M 3
    :FEAT :FPU
    D9 FLDLG2
    :REG 5
    :MOD 3
    :R/M 4
    :FEAT :FPU
    D9 FLDLN2
    :REG 5
    :MOD 3
    :R/M 5
    :FEAT :FPU
    D9 FLDZ
    :REG 5
    :MOD 3
    :R/M 6
    :FEAT :FPU