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      • Program-execution
      • Sdm-instruction-set-summary
        • 5.50 Uncategorized "Instructions"
        • 5.15 Fused-Multiply-Add (FMA)
        • 5.20 System Instructions
        • 5.19 Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)
        • 5.1 General-Purpose Instructions
          • 5.1.2 Binary Arithmetic Instructions
          • 5.1.1 Data Transfer Instructions
          • 5.1.16 BMI1 and BMI2 Instructions
          • 5.1.5 Shift and Rotate Instructions
          • 5.1.4 Logical Instructions
          • 5.1.7 Control Transfer Instructions
          • 5.1.6 Bit and Byte Instructions
          • 5.1.13 Miscellaneous Instructions
          • 5.1.15 Random Number Generator Instructions
          • 5.1.8 String Instructions
          • 5.1.9 I/O Instructions
          • 5.1.14 User Mode Extended State Save/Restore Instructions
          • 5.1.11 Flag Control (EFLAG) Instructions
          • 5.1.10 Enter and Leave Instructions
          • 5.1.3 Decimal Arithmetic Instructions
          • 5.1.12 Segment Register Instructions
        • 5.10 Intel(R) SSE4.1 Instructions
        • 5.13 Intel(R) Advanced Vector Extensions (Intel(R) AVX)
        • 5.7 Intel(R) SSE3 Instructions
        • 5.8 Supplemental Streaming Simd Extensions 3 (SSSE3) Instructions
        • 5.4 MMX Instructions
        • 5.22 Virtual-Machine Extensions
        • 5.6 Intel(R) SSE2 Instructions
        • 5.21 64-Bit Mode Instructions
        • 5.2 X87 FPU Instructions
        • 5.24 Intel(R) Memory Protection Extensions
        • 5.5 Intel(R) SSE Instructions
        • 5.16 Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2)
        • 5.12 Intel(R) AES-NI And PCLMULQDQ
        • 5.17 Intel(R) Transactional Synchronization Extensions (Intel(R) Tsx)
        • 5.14 16-Bit Floating-Point Conversion
        • 5.18 Intel(R) SHA Extensions
        • 5.11 Intel(R) SSE4.2 Instruction Set
        • 5.3 X87 FPU and SIMD State Management Instructions
        • 5.40 Other ISA Extensions
        • 5.25 Intel(R) Software Guard Extensions
        • 5.27 Control Transfer Terminating Instructions
        • 5.23 Safer Mode Extensions
        • 5.30 Enqueue Store Instructions
        • 5.29 User Interrupt Instructions
        • 5.28 Intel(R) AMX Instructions
        • 5.26 Shadow Stack Management Instructions
        • 5.31 Intel(R) Advanced Vector Extensions 10 Version 1 Instructions
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  • Testing-utilities

• 5.1 General-Purpose Instructions

5.1.6 Bit and Byte Instructions

Unimplemented instructions are:

• POPCNT
• BTC
• CRC32

Unimplemented Instructions

Opcode	Mnemonic	Other Information	Semantic Function
0F BB	BTC
F2 0F 38 F0	CRC32	:PFX :F2 :FEAT :SSE4.2
F2 0F 38 F1	CRC32	:PFX :F2 :FEAT :SSE4.2

Implemented Instructions

Opcode	Mnemonic	Other Information	Semantic Function
84	TEST		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x7))
85	TEST		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x7))
A8	TEST		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x7))
A9	TEST		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x7))
F6	TEST	:REG 0	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x7))
F7	TEST	:REG 0	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x7))
0F 90	SETO		x86-setcc
0F 91	SETNO		x86-setcc
0F 92	SETB/NAE/C		x86-setcc
0F 93	SETNB/AE/NC		x86-setcc
0F 94	SETZ/E		x86-setcc
0F 95	SETNZ/NE		x86-setcc
0F 96	SETBE/NA		x86-setcc
0F 97	SETNBE/A		x86-setcc
0F 98	SETS		x86-setcc
0F 99	SETNS		x86-setcc
0F 9A	SETP/PE		x86-setcc
0F 9B	SETNP/PO		x86-setcc
0F 9C	SETL/NGE		x86-setcc
0F 9D	SETNL/GE		x86-setcc
0F 9E	SETLE/NG		x86-setcc
0F 9F	SETNLE/G		x86-setcc
0F A3	BT		x86-bt-0f-a3
0F AB	BTS		x86-bt-0f-ab
0F B3	BTR		x86-btr-0f-b3
F3 0F B8	POPCNT	:PFX :F3 :FEAT :POPCNT	x86-popcnt
0F BA	BT	:REG 4	x86-bt-0f-ba
0F BA	BTS	:REG 5	x86-bt-0f-ba
0F BA	BTR	:REG 6	x86-bt-0f-ba
0F BA	BTC	:REG 7	x86-bt-0f-ba
NP 0F BC	BSF	:PFX :NO-PREFIX	x86-bsf-op/en-rm
NP 0F BD	BSR	:PFX :NO-PREFIX	x86-bsr