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      • Program-execution
      • Sdm-instruction-set-summary
        • 5.50 Uncategorized "Instructions"
        • 5.15 Fused-Multiply-Add (FMA)
        • 5.20 System Instructions
        • 5.19 Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)
        • 5.1 General-Purpose Instructions
          • 5.1.2 Binary Arithmetic Instructions
          • 5.1.1 Data Transfer Instructions
          • 5.1.16 BMI1 and BMI2 Instructions
          • 5.1.5 Shift and Rotate Instructions
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          • 5.1.13 Miscellaneous Instructions
          • 5.1.15 Random Number Generator Instructions
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          • 5.1.9 I/O Instructions
          • 5.1.14 User Mode Extended State Save/Restore Instructions
          • 5.1.11 Flag Control (EFLAG) Instructions
          • 5.1.10 Enter and Leave Instructions
          • 5.1.3 Decimal Arithmetic Instructions
          • 5.1.12 Segment Register Instructions
        • 5.10 Intel(R) SSE4.1 Instructions
        • 5.13 Intel(R) Advanced Vector Extensions (Intel(R) AVX)
        • 5.7 Intel(R) SSE3 Instructions
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        • 5.4 MMX Instructions
        • 5.22 Virtual-Machine Extensions
        • 5.6 Intel(R) SSE2 Instructions
        • 5.21 64-Bit Mode Instructions
        • 5.2 X87 FPU Instructions
        • 5.24 Intel(R) Memory Protection Extensions
        • 5.5 Intel(R) SSE Instructions
        • 5.16 Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2)
        • 5.12 Intel(R) AES-NI And PCLMULQDQ
        • 5.17 Intel(R) Transactional Synchronization Extensions (Intel(R) Tsx)
        • 5.14 16-Bit Floating-Point Conversion
        • 5.18 Intel(R) SHA Extensions
        • 5.11 Intel(R) SSE4.2 Instruction Set
        • 5.3 X87 FPU and SIMD State Management Instructions
        • 5.40 Other ISA Extensions
        • 5.25 Intel(R) Software Guard Extensions
        • 5.27 Control Transfer Terminating Instructions
        • 5.23 Safer Mode Extensions
        • 5.30 Enqueue Store Instructions
        • 5.29 User Interrupt Instructions
        • 5.28 Intel(R) AMX Instructions
        • 5.26 Shadow Stack Management Instructions
        • 5.31 Intel(R) Advanced Vector Extensions 10 Version 1 Instructions
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• 5.1 General-Purpose Instructions

5.1.2 Binary Arithmetic Instructions

The only unimplemented instructions are ADCX and ADOX, which set CF and OF flags differently from the more typical ADD/ADC operations.

Implemented Instructions

Opcode	Mnemonic	Other Information	Semantic Function
	ADD		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x0))
01	ADD		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x0))
02	ADD		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x0))
03	ADD		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x0))
04	ADD		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x0))
05	ADD		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x0))
10	ADC		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x2))
11	ADC		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x2))
12	ADC		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x2))
13	ADC		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x2))
14	ADC		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x2))
15	ADC		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x2))
18	SBB		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x6))
19	SBB		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x6))
1A	SBB		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x6))
1B	SBB		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x6))
1C	SBB		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x6))
1D	SBB		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x6))
28	SUB		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x4))
29	SUB		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x4))
2A	SUB		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x4))
2B	SUB		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x4))
2C	SUB		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x4))
2D	SUB		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x4))
38	CMP		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x8))
39	CMP		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x8))
3A	CMP		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x8))
3B	CMP		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x8))
3C	CMP		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x8))
3D	CMP		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x8))
40	INC	:MODE :I64	x86-inc/dec-4x
41	INC	:MODE :I64	x86-inc/dec-4x
42	INC	:MODE :I64	x86-inc/dec-4x
43	INC	:MODE :I64	x86-inc/dec-4x
44	INC	:MODE :I64	x86-inc/dec-4x
45	INC	:MODE :I64	x86-inc/dec-4x
46	INC	:MODE :I64	x86-inc/dec-4x
47	INC	:MODE :I64	x86-inc/dec-4x
48	DEC	:MODE :I64	x86-inc/dec-4x
49	DEC	:MODE :I64	x86-inc/dec-4x
4A	DEC	:MODE :I64	x86-inc/dec-4x
4B	DEC	:MODE :I64	x86-inc/dec-4x
4C	DEC	:MODE :I64	x86-inc/dec-4x
4D	DEC	:MODE :I64	x86-inc/dec-4x
4E	DEC	:MODE :I64	x86-inc/dec-4x
4F	DEC	:MODE :I64	x86-inc/dec-4x
69	IMUL		x86-imul-op/en-rmi
6B	IMUL		x86-imul-op/en-rmi
80	ADD	:REG 0	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x0))
80	ADC	:REG 2	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x2))
80	SBB	:REG 3	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x6))
80	SUB	:REG 5	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x4))
80	CMP	:REG 7	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x8))
81	ADD	:REG 0	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x0))
81	ADC	:REG 2	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x2))
81	SBB	:REG 3	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x6))
81	SUB	:REG 5	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x4))
81	CMP	:REG 7	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x8))
82	ADD	:MODE :I64 :REG 0	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x0))
82	ADC	:MODE :I64 :REG 2	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x2))
82	SBB	:MODE :I64 :REG 3	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x6))
82	SUB	:MODE :I64 :REG 5	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x4))
82	CMP	:MODE :I64 :REG 7	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x8))
83	ADD	:REG 0	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x0))
83	ADC	:REG 2	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x2))
83	SBB	:REG 3	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x6))
83	SUB	:REG 5	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x4))
83	CMP	:REG 7	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x8))
F6	NEG	:REG 3	x86-not/neg-f6-f7
F6	MUL	:REG 4	x86-mul
F6	IMUL	:REG 5	x86-imul-op/en-m
F6	DIV	:REG 6	x86-div
F6	IDIV	:REG 7	x86-idiv
F7	NEG	:REG 3	x86-not/neg-f6-f7
F7	MUL	:REG 4	x86-mul
F7	IMUL	:REG 5	x86-imul-op/en-m
F7	DIV	:REG 6	x86-div
F7	IDIV	:REG 7	x86-idiv
FE	INC	:REG 0	x86-inc/dec-fe-ff
FE	DEC	:REG 1	x86-inc/dec-fe-ff
FF	INC	:REG 0	x86-inc/dec-fe-ff
FF	DEC	:REG 1	x86-inc/dec-fe-ff
0F AF	IMUL		x86-imul-op/en-rm
66 0F 38 F6	ADCX	:PFX :66 :FEAT :ADX	x86-adcx/adox -- ((adcx . t))
F3 0F 38 F6	ADOX	:PFX :F3 :FEAT :ADX	x86-adcx/adox -- ((adcx))