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        • Sdm-instruction-set-summary
          • 5.50 Uncategorized "Instructions"
          • 5.15 Fused-Multiply-Add (FMA)
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          • 5.19 Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)
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          • 5.4 MMX Instructions
          • 5.22 Virtual-Machine Extensions
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          • 5.21 64-Bit Mode Instructions
          • 5.2 X87 FPU Instructions
          • 5.24 Intel(R) Memory Protection Extensions
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          • 5.16 Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2)
          • 5.12 Intel(R) AES-NI And PCLMULQDQ
          • 5.17 Intel(R) Transactional Synchronization Extensions (Intel(R) Tsx)
          • 5.14 16-Bit Floating-Point Conversion
          • 5.18 Intel(R) SHA Extensions
          • 5.11 Intel(R) SSE4.2 Instruction Set
          • 5.3 X87 FPU and SIMD State Management Instructions
          • 5.40 Other ISA Extensions
          • 5.25 Intel(R) Software Guard Extensions
          • 5.27 Control Transfer Terminating Instructions
          • 5.23 Safer Mode Extensions
          • 5.30 Enqueue Store Instructions
          • 5.29 User Interrupt Instructions
          • 5.28 Intel(R) AMX Instructions
          • 5.26 Shadow Stack Management Instructions
          • 5.31 Intel(R) Advanced Vector Extensions 10 Version 1 Instructions
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  • X86isa

Sdm-instruction-set-summary

Summary of what instructions are implemented/unimplemented, as organized in the Instruction Set Summary of the Intel Software Developer Manual (volume 1 chapter 5).

Note: this summary is based on the opcode maps (see implemented-opcodes and subtopics). To the extent that the opcode maps are incomplete (as noted in several of the below topics), the instruction counts listed below and in subtopics are as well.

Subsections

Total instructions: 3266, Implemented: 700, Unimplemented: 2566

Subsection Implemented Unimplemented Total
5.1 General-Purpose Instructions38570455
5.2 X87 FPU Instructions1126127
5.3 X87 FPU and SIMD State Management Instructions202
5.4 MMX Instructions35457
5.5 Intel(R) SSE Instructions452671
5.6 Intel(R) SSE2 Instructions10145146
5.7 Intel(R) SSE3 Instructions11415
5.8 Supplemental Streaming Simd Extensions 3 (SSSE3) Instructions03232
5.10 Intel(R) SSE4.1 Instructions06363
5.11 Intel(R) SSE4.2 Instruction Set055
5.12 Intel(R) AES-NI And PCLMULQDQ077
5.13 Intel(R) Advanced Vector Extensions (Intel(R) AVX)66346412
5.14 16-Bit Floating-Point Conversion044
5.15 Fused-Multiply-Add (FMA)09696
5.16 Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2)19152171
5.17 Intel(R) Transactional Synchronization Extensions (Intel(R) Tsx)044
5.18 Intel(R) SHA Extensions077
5.19 Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)014411441
5.20 System Instructions103343
5.21 64-Bit Mode Instructions10111
5.22 Virtual-Machine Extensions01313
5.23 Safer Mode Extensions011
5.24 Intel(R) Memory Protection Extensions01010
5.25 Intel(R) Software Guard Extensions022
5.26 Shadow Stack Management Instructions000
5.27 Control Transfer Terminating Instructions101
5.28 Intel(R) AMX Instructions000
5.29 User Interrupt Instructions000
5.30 Enqueue Store Instructions000
5.31 Intel(R) Advanced Vector Extensions 10 Version 1 Instructions000
5.40 Other ISA Extensions022
5.50 Uncategorized "Instructions"561268

Subtopics

5.50 Uncategorized "Instructions"
5.15 Fused-Multiply-Add (FMA)
5.20 System Instructions
5.19 Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)
5.1 General-Purpose Instructions
5.10 Intel(R) SSE4.1 Instructions
5.13 Intel(R) Advanced Vector Extensions (Intel(R) AVX)
5.7 Intel(R) SSE3 Instructions
5.8 Supplemental Streaming Simd Extensions 3 (SSSE3) Instructions
5.4 MMX Instructions
5.22 Virtual-Machine Extensions
5.6 Intel(R) SSE2 Instructions
5.21 64-Bit Mode Instructions
5.2 X87 FPU Instructions
5.24 Intel(R) Memory Protection Extensions
5.5 Intel(R) SSE Instructions
5.16 Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2)
5.12 Intel(R) AES-NI And PCLMULQDQ
5.17 Intel(R) Transactional Synchronization Extensions (Intel(R) Tsx)
5.14 16-Bit Floating-Point Conversion
5.18 Intel(R) SHA Extensions
5.11 Intel(R) SSE4.2 Instruction Set
5.3 X87 FPU and SIMD State Management Instructions
5.40 Other ISA Extensions
5.25 Intel(R) Software Guard Extensions
5.27 Control Transfer Terminating Instructions
5.23 Safer Mode Extensions
5.30 Enqueue Store Instructions
5.29 User Interrupt Instructions
5.28 Intel(R) AMX Instructions
5.26 Shadow Stack Management Instructions
5.31 Intel(R) Advanced Vector Extensions 10 Version 1 Instructions