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        • 5.50 Uncategorized "Instructions"
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          • 5.6.10 Intel(R) SSE2 Instructions Promoted from Previous Extensions (and not listed previously)
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          • 5.6.4 Intel(R) SSE2 Cacheability Control and Ordering Instructions
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• Sdm-instruction-set-summary

5.6 Intel(R) SSE2 Instructions

Subsections

Total instructions: 146, Implemented: 101, Unimplemented: 45

Subsection	Implemented	Unimplemented	Total
5.6.1 Intel(R) SSE2 Packed and Scalar Double Precision Floating-Point Instructions	42	7	49
5.6.2 Intel(R) SSE2 Packed Single Precision Floating-Point Instructions	0	3	3
5.6.3 Intel(R) SSE2 128-Bit SIMD Integer Instructions	14	5	19
5.6.4 Intel(R) SSE2 Cacheability Control and Ordering Instructions	1	6	7
5.6.10 Intel(R) SSE2 Instructions Promoted from Previous Extensions (and not listed previously)	44	24	68

Subtopics

5.6.10 Intel(R) SSE2 Instructions Promoted from Previous Extensions (and not listed previously)

5.6.3 Intel(R) SSE2 128-Bit SIMD Integer Instructions

5.6.4 Intel(R) SSE2 Cacheability Control and Ordering Instructions

5.6.1 Intel(R) SSE2 Packed and Scalar Double Precision Floating-Point Instructions

5.6.2 Intel(R) SSE2 Packed Single Precision Floating-Point Instructions