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• Parse-statements

Vl-parse-case-statement

Parse case_statement into a vl-stmt-p.

Signature

(vl-parse-case-statement atts &key (tokstream 'tokstream) 
                         (config 'config)) 
 
  → 
(mv errmsg? value new-tokstream)

Arguments

config — Guard (vl-loadconfig-p config).

Verilog-2005 Syntax:

case_statement ::=
     'case' '(' expression ')' case_item {case_item} 'endcase'
   | 'casez' '(' expression ')' case_item {case_item} 'endcase'
   | 'casex' '(' expression ')' case_item {case_item} 'endcase'

SystemVerilog-2012 extends this kind of basic case statement with optional unique, priority and priority0 keywords:

case_statement ::= [unique_priority]
                   case_keyword '(' expression ')' case_item {case_item} 'endcase'
                 | ...

case_keyword ::= 'case' | 'casez' | 'casex'
unique_priority ::= 'unique' | 'unique0' | 'priority'

So the above is the same across Verilog-2005 and SystemVerilog-2012 except for the optional unique_priority.

SystemVerilog also adds new case matches and case inside statements:

case_statement ::= ...
                 | [unique_priority] case_keyword '(' expression ')'
                      'matches' case_pattern_item {case_pattern_item} 'endcase'
                 | [unique_priority] 'case' '(' expression ')'
                      'inside' case_inside_item {case_inside_item} 'endcase'

But BOZO we do not yet implement these.