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• Parse-statements

Vl-parse-statement-2005-aux

Verilog-2005 Only. Main part of statement parsing.

Signature

(vl-parse-statement-2005-aux atts &key (tokstream 'tokstream) 
                             (config 'config)) 
 
  → 
(mv errmsg? value new-tokstream)

Arguments

config — Guard (vl-loadconfig-p config).

Here's the Verilog-2005 statement rule:

statement ::=                                                      ;;; starts with
   {attribute_instance} blocking_assignment ';'                    ;;; <complicated>
 | {attribute_instance} case_statement                             ;;; 'case', 'casez', 'casex'
 | {attribute_instance} conditional_statement                      ;;; 'if'
 | {attribute_instance} disable_statement                          ;;; 'disable'
 | {attribute_instance} event_trigger                              ;;; '->'
 | {attribute_instance} loop_statement                             ;;; 'forever', 'repeat', 'while', 'for'
 | {attribute_instance} nonblocking_assignment ';'                 ;;; <complicated>
 | {attribute_instance} par_block                                  ;;; 'fork'
 | {attribute_instance} procedural_continuous_assignments ';'      ;;; 'assign', 'deassign', 'force', 'release'
 | {attribute_instance} procedural_timing_control_statement        ;;; '#', '@'
 | {attribute_instance} seq_block                                  ;;; 'begin'
 | {attribute_instance} system_task_enable                         ;;; sysidtoken
 | {attribute_instance} task_enable                                ;;; <complicated>
 | {attribute_instance} wait_statement                             ;;; 'wait'

Here we assume we have already parsed the attributes and we are just wanting to parse the main part of the statement.