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      • X86isa
        • Program-execution
        • Sdm-instruction-set-summary
          • 5.50 Uncategorized "Instructions"
          • 5.15 Fused-Multiply-Add (FMA)
          • 5.20 System Instructions
          • 5.19 Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)
          • 5.1 General-Purpose Instructions
            • 5.1.2 Binary Arithmetic Instructions
            • 5.1.1 Data Transfer Instructions
              • 5.1.16 BMI1 and BMI2 Instructions
              • 5.1.5 Shift and Rotate Instructions
              • 5.1.4 Logical Instructions
              • 5.1.7 Control Transfer Instructions
              • 5.1.6 Bit and Byte Instructions
              • 5.1.13 Miscellaneous Instructions
              • 5.1.15 Random Number Generator Instructions
              • 5.1.8 String Instructions
              • 5.1.9 I/O Instructions
              • 5.1.14 User Mode Extended State Save/Restore Instructions
              • 5.1.11 Flag Control (EFLAG) Instructions
              • 5.1.10 Enter and Leave Instructions
              • 5.1.3 Decimal Arithmetic Instructions
              • 5.1.12 Segment Register Instructions
            • 5.10 Intel(R) SSE4.1 Instructions
            • 5.13 Intel(R) Advanced Vector Extensions (Intel(R) AVX)
            • 5.7 Intel(R) SSE3 Instructions
            • 5.8 Supplemental Streaming Simd Extensions 3 (SSSE3) Instructions
            • 5.4 MMX Instructions
            • 5.22 Virtual-Machine Extensions
            • 5.6 Intel(R) SSE2 Instructions
            • 5.21 64-Bit Mode Instructions
            • 5.2 X87 FPU Instructions
            • 5.24 Intel(R) Memory Protection Extensions
            • 5.5 Intel(R) SSE Instructions
            • 5.16 Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2)
            • 5.12 Intel(R) AES-NI And PCLMULQDQ
            • 5.17 Intel(R) Transactional Synchronization Extensions (Intel(R) Tsx)
            • 5.14 16-Bit Floating-Point Conversion
            • 5.18 Intel(R) SHA Extensions
            • 5.11 Intel(R) SSE4.2 Instruction Set
            • 5.3 X87 FPU and SIMD State Management Instructions
            • 5.40 Other ISA Extensions
            • 5.25 Intel(R) Software Guard Extensions
            • 5.27 Control Transfer Terminating Instructions
            • 5.23 Safer Mode Extensions
            • 5.30 Enqueue Store Instructions
            • 5.29 User Interrupt Instructions
            • 5.28 Intel(R) AMX Instructions
            • 5.26 Shadow Stack Management Instructions
            • 5.31 Intel(R) Advanced Vector Extensions 10 Version 1 Instructions
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    • 5.1 General-Purpose Instructions

    5.1.1 Data Transfer Instructions

    Unimplemented instructions are:

    • POP variants that write to segment registers: these have side effects, perhaps similar to those of MOV to a segment register
    • CMPEXCHG8B

    Unimplemented Instructions

    Opcode Mnemonic Other Information Semantic Function
    07 POP ES
    :MODE :I64
    17 POP SS
    :MODE :I64
    1F POP DS
    :MODE :I64
    0F A1 POP
    0F A9 POP

    Implemented Instructions

    Opcode Mnemonic Other Information Semantic Function
    06 PUSH ES
    :MODE :I64
    x86-push-segment-register
    0E PUSH CS
    :MODE :I64
    x86-push-segment-register
    16 PUSH SS
    :MODE :I64
    x86-push-segment-register
    1E PUSH DS
    :MODE :I64
    x86-push-segment-register
    50 PUSH
    x86-push-general-register
    51 PUSH
    x86-push-general-register
    52 PUSH
    x86-push-general-register
    53 PUSH
    x86-push-general-register
    54 PUSH
    x86-push-general-register
    55 PUSH
    x86-push-general-register
    56 PUSH
    x86-push-general-register
    57 PUSH
    x86-push-general-register
    58 POP
    x86-pop-general-register
    59 POP
    x86-pop-general-register
    5A POP
    x86-pop-general-register
    5B POP
    x86-pop-general-register
    5C POP
    x86-pop-general-register
    5D POP
    x86-pop-general-register
    5E POP
    x86-pop-general-register
    5F POP
    x86-pop-general-register
    60 PUSHA/PUSHAD
    :MODE :I64
    x86-pusha
    61 POPA/POPAD
    :MODE :I64
    x86-popa
    63 MOVSXD
    :MODE :O64
    x86-movsxd
    68 PUSH
    x86-push-i
    6A PUSH
    x86-push-i
    86 XCHG
    x86-xchg
    87 XCHG
    x86-xchg
    88 MOV
    x86-mov-op/en-mr
    89 MOV
    x86-mov-op/en-mr
    8A MOV
    x86-mov-op/en-rm
    8B MOV
    x86-mov-op/en-rm
    8C MOV
    x86-mov-op/en-mr
    8E MOV
    x86-mov-op/en-rm
    8F POP
    :REG 0
    x86-pop-ev
    90 XCHG
    x86-xchg
    91 XCHG
    x86-xchg
    92 XCHG
    x86-xchg
    93 XCHG
    x86-xchg
    94 XCHG
    x86-xchg
    95 XCHG
    x86-xchg
    96 XCHG
    x86-xchg
    97 XCHG
    x86-xchg
    98 CBW/CWDE/CDQE
    x86-cbw/cwd/cdqe
    99 CWD/CDQ/CQO
    x86-cwd/cdq/cqo
    A0 MOV
    x86-mov-op/en-fd
    A1 MOV
    x86-mov-op/en-fd
    A2 MOV
    x86-mov-op/en-td
    A3 MOV
    x86-mov-op/en-td
    B0 MOV
    x86-mov-op/en-oi
    B1 MOV
    x86-mov-op/en-oi
    B2 MOV
    x86-mov-op/en-oi
    B3 MOV
    x86-mov-op/en-oi
    B4 MOV
    x86-mov-op/en-oi
    B5 MOV
    x86-mov-op/en-oi
    B6 MOV
    x86-mov-op/en-oi
    B7 MOV
    x86-mov-op/en-oi
    B8 MOV
    x86-mov-op/en-oi
    B9 MOV
    x86-mov-op/en-oi
    BA MOV
    x86-mov-op/en-oi
    BB MOV
    x86-mov-op/en-oi
    BC MOV
    x86-mov-op/en-oi
    BD MOV
    x86-mov-op/en-oi
    BE MOV
    x86-mov-op/en-oi
    BF MOV
    x86-mov-op/en-oi
    C6 MOV
    :REG 0
    x86-mov-op/en-mi
    C7 MOV
    :REG 0
    x86-mov-op/en-mi
    FF PUSH
    :REG 6
    x86-push-ev
    0F 20 MOV
    x86-mov-control-regs-op/en-mr
    0F 21 MOV
    x86-two-byte-nop
    0F 22 MOV
    x86-mov-control-regs-op/en-rm
    0F 23 MOV
    x86-two-byte-nop
    0F 40 CMOVO
    x86-cmovcc
    0F 41 CMOVNO
    x86-cmovcc
    0F 42 CMOVB/C/NAE
    x86-cmovcc
    0F 43 CMOVAE/NB/NC
    x86-cmovcc
    0F 44 CMOVE/Z
    x86-cmovcc
    0F 45 CMOVNE/NZ
    x86-cmovcc
    0F 46 CMOVBE/NA
    x86-cmovcc
    0F 47 CMOVA/NBE
    x86-cmovcc
    0F 48 CMOVS
    x86-cmovcc
    0F 49 CMOVNS
    x86-cmovcc
    0F 4A CMOVP/PE
    x86-cmovcc
    0F 4B CMOVNP/PO
    x86-cmovcc
    0F 4C CMOVL/NGE
    x86-cmovcc
    0F 4D CMOVNL/GE
    x86-cmovcc
    0F 4E CMOVLE/NG
    x86-cmovcc
    0F 4F CMOVNLE/G
    x86-cmovcc
    0F A0 PUSH FS
    x86-push-segment-register
    0F A8 PUSH GS
    x86-push-segment-register
    0F B0 CMPXCHG
    x86-cmpxchg
    0F B1 CMPXCHG
    x86-cmpxchg
    0F B6 MOVZX
    x86-movzx
    0F B7 MOVZX
    x86-movzx
    0F BE MOVSX
    x86-movsx
    0F BF MOVSX
    x86-movsx
    0F C0 XADD
    x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g --
    ((operation . #x26))
    0F C1 XADD
    x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g --
    ((operation . #x26))
    NP 0F C7 CMPXCHG8B
    :PFX :NO-PREFIX
    :REG 1
    :MOD :MEM
    :REX :NOT-W
    :FEAT :CMPXCHG16B
    x86-cmpxchg8b/16b
    0F C8 BSWAP
    x86-bswap
    0F C9 BSWAP
    x86-bswap
    0F CA BSWAP
    x86-bswap
    0F CB BSWAP
    x86-bswap
    0F CC BSWAP
    x86-bswap
    0F CD BSWAP
    x86-bswap
    0F CE BSWAP
    x86-bswap
    0F CF BSWAP
    x86-bswap