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Occform

vl-1-bit-adder-core

Primitive one-bit full-adder module.

A full-adder is a one-bit adder that produces a sum and carry. We use the following definition:

module VL_1_BIT_ADDER_CORE (sum, cout, a, b, cin) ;
  output sum, cout;
  input a, b, cin;
  wire t1, t2, t3;

  assign t1 = a ^ b;
  assign sum = t1 ^ cin;
  assign t2 = t1 & cin;
  assign t3 = a & b;
  assign cout = t2 | t3;

endmodule

This is only a "core." It doesn't quite correspond to an addition like assign {carry, sum} = a + b + cin in Verilog because of X handling. See vl-make-n-bit-plusminus for the real module generator.

Definition: *vl-1-bit-adder-core*

(defconst *vl-1-bit-adder-core*
 (b*
  ((name (hons-copy "VL_1_BIT_ADDER_CORE"))
   ((mv sum-expr
        sum-port sum-portdecl sum-vardecl)
    (vl-primitive-mkport "sum" :vl-output))
   ((mv cout-expr
        cout-port cout-portdecl cout-vardecl)
    (vl-primitive-mkport "cout" :vl-output))
   ((mv a-expr a-port a-portdecl a-vardecl)
    (vl-primitive-mkport "a" :vl-input))
   ((mv b-expr b-port b-portdecl b-vardecl)
    (vl-primitive-mkport "b" :vl-input))
   ((mv cin-expr
        cin-port cin-portdecl cin-vardecl)
    (vl-primitive-mkport "cin" :vl-input))
   ((mv t1-expr t1-vardecl)
    (vl-primitive-mkwire "t1"))
   ((mv t2-expr t2-vardecl)
    (vl-primitive-mkwire "t2"))
   ((mv t3-expr t3-vardecl)
    (vl-primitive-mkwire "t3"))
   (t1-inst (vl-simple-inst *vl-1-bit-xor*
                            "mk_t1" t1-expr a-expr b-expr))
   (sum-inst (vl-simple-inst *vl-1-bit-xor*
                             "mk_sum" sum-expr t1-expr cin-expr))
   (t2-inst (vl-simple-inst *vl-1-bit-and*
                            "mk_t2" t2-expr t1-expr cin-expr))
   (t3-inst (vl-simple-inst *vl-1-bit-and*
                            "mk_t3" t3-expr a-expr b-expr))
   (cout-inst (vl-simple-inst *vl-1-bit-or*
                              "mk_cout" cout-expr t2-expr t3-expr)))
  (hons-copy
       (make-vl-module
            :name name
            :origname name
            :ports (list sum-port
                         cout-port a-port b-port cin-port)
            :portdecls (list sum-portdecl cout-portdecl
                             a-portdecl b-portdecl cin-portdecl)
            :vardecls (list sum-vardecl cout-vardecl
                            a-vardecl b-vardecl cin-vardecl
                            t1-vardecl t2-vardecl t3-vardecl)
            :modinsts (list t1-inst
                            sum-inst t2-inst t3-inst cout-inst)
            :minloc *vl-fakeloc*
            :maxloc *vl-fakeloc*))))

Subtopics

*vl-1-bit-adder-core-support*