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      • Program-execution
      • Sdm-instruction-set-summary
        • 5.50 Uncategorized "Instructions"
        • 5.15 Fused-Multiply-Add (FMA)
        • 5.20 System Instructions
        • 5.19 Intel(R) Advanced Vector Extensions 512 (Intel(R) AVX-512)
        • 5.1 General-Purpose Instructions
          • 5.1.2 Binary Arithmetic Instructions
          • 5.1.1 Data Transfer Instructions
          • 5.1.16 BMI1 and BMI2 Instructions
          • 5.1.5 Shift and Rotate Instructions
          • 5.1.4 Logical Instructions
          • 5.1.7 Control Transfer Instructions
          • 5.1.6 Bit and Byte Instructions
          • 5.1.13 Miscellaneous Instructions
          • 5.1.15 Random Number Generator Instructions
          • 5.1.8 String Instructions
          • 5.1.9 I/O Instructions
          • 5.1.14 User Mode Extended State Save/Restore Instructions
          • 5.1.11 Flag Control (EFLAG) Instructions
          • 5.1.10 Enter and Leave Instructions
          • 5.1.3 Decimal Arithmetic Instructions
          • 5.1.12 Segment Register Instructions
        • 5.10 Intel(R) SSE4.1 Instructions
        • 5.13 Intel(R) Advanced Vector Extensions (Intel(R) AVX)
        • 5.7 Intel(R) SSE3 Instructions
        • 5.8 Supplemental Streaming Simd Extensions 3 (SSSE3) Instructions
        • 5.4 MMX Instructions
        • 5.22 Virtual-Machine Extensions
        • 5.6 Intel(R) SSE2 Instructions
        • 5.21 64-Bit Mode Instructions
        • 5.2 X87 FPU Instructions
        • 5.24 Intel(R) Memory Protection Extensions
        • 5.5 Intel(R) SSE Instructions
        • 5.16 Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2)
        • 5.12 Intel(R) AES-NI And PCLMULQDQ
        • 5.17 Intel(R) Transactional Synchronization Extensions (Intel(R) Tsx)
        • 5.14 16-Bit Floating-Point Conversion
        • 5.18 Intel(R) SHA Extensions
        • 5.11 Intel(R) SSE4.2 Instruction Set
        • 5.3 X87 FPU and SIMD State Management Instructions
        • 5.40 Other ISA Extensions
        • 5.25 Intel(R) Software Guard Extensions
        • 5.27 Control Transfer Terminating Instructions
        • 5.23 Safer Mode Extensions
        • 5.30 Enqueue Store Instructions
        • 5.29 User Interrupt Instructions
        • 5.28 Intel(R) AMX Instructions
        • 5.26 Shadow Stack Management Instructions
        • 5.31 Intel(R) Advanced Vector Extensions 10 Version 1 Instructions
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• 5.1 General-Purpose Instructions

5.1.4 Logical Instructions

Implemented Instructions

Opcode	Mnemonic	Other Information	Semantic Function
08	OR		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x1))
09	OR		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x1))
0A	OR		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x1))
0B	OR		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x1))
0C	OR		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x1))
0D	OR		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x1))
20	AND		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x3))
21	AND		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x3))
22	AND		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x3))
23	AND		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x3))
24	AND		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x3))
25	AND		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x3))
30	XOR		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x5))
31	XOR		x86-add/xadd/adc/sub/sbb/or/and/xor/cmp/test-e-g -- ((operation . #x5))
32	XOR		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x5))
33	XOR		x86-add/adc/sub/sbb/or/and/xor/cmp-g-e -- ((operation . #x5))
34	XOR		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x5))
35	XOR		x86-add/adc/sub/sbb/or/and/xor/cmp-test-rax-i -- ((operation . #x5))
80	OR	:REG 1	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x1))
80	AND	:REG 4	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x3))
80	XOR	:REG 6	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x5))
81	OR	:REG 1	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x1))
81	AND	:REG 4	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x3))
81	XOR	:REG 6	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x5))
82	OR	:MODE :I64 :REG 1	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x1))
82	AND	:MODE :I64 :REG 4	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x3))
82	XOR	:MODE :I64 :REG 6	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x5))
83	OR	:REG 1	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x1))
83	AND	:REG 4	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x3))
83	XOR	:REG 6	x86-add/adc/sub/sbb/or/and/xor/cmp-test-e-i -- ((operation . #x5))
F6	NOT	:REG 2	x86-not/neg-f6-f7
F7	NOT	:REG 2	x86-not/neg-f6-f7