• Top
    • Documentation
    • Books
    • Boolean-reasoning
    • Projects
    • Debugging
    • Community
    • Std
    • Proof-automation
    • Macro-libraries
    • ACL2
    • Interfacing-tools
    • Hardware-verification
      • Gl
      • Esim
      • Vl2014
        • Warnings
        • Primitives
        • Use-set
        • Syntax
        • Getting-started
        • Utilities
        • Loader
        • Transforms
          • Expression-sizing
          • Occform
          • Oprewrite
          • Expand-functions
          • Delayredux
          • Unparameterization
          • Caseelim
          • Split
          • Selresolve
          • Weirdint-elim
          • Vl-delta
          • Replicate-insts
          • Rangeresolve
          • Propagate
          • Clean-selects
          • Clean-params
          • Blankargs
          • Inline-mods
          • Expr-simp
          • Trunc
          • Always-top
            • Edgesynth
            • Stmtrewrite
              • Vl-modulelist-stmtrewrite
              • Vl-blockstmt-rewrite
              • Vl-repeatstmt-rewrite
              • Vl-flatten-blocks
              • Vl-stmt-rewrite-top
              • Vl-casestmt-rewrite
              • Vl-stmt-rewrite
              • Vl-waitstmt-rewrite
              • Vl-ifstmt-combine-rewrite
                • Vl-forstmt-rewrite
                • Vl-initiallist-stmtrewrite
                • Vl-alwayslist-stmtrewrite
                • Vl-initial-stmtrewrite
                • Vl-foreverstmt-rewrite
                • Vl-always-stmtrewrite
                • Vl-module-stmtrewrite
                • Vl-design-stmtrewrite
                • Vl-remove-null-statements
                • Vl-$vcover-stmt-p
                • Vl-$display-stmt-p
                • Vl-caselist-all-null-p
              • Cblock
              • Vl-always-convert-regports
              • Vl-always-convert-regs
              • Stmttemps
              • Edgesplit
              • Vl-always-check-reg
              • Vl-convert-regs
              • Latchsynth
              • Vl-always-check-regs
              • Vl-match-always-at-some-edges
              • Unelse
              • Vl-always-convert-reg
              • Vl-design-always-backend
              • Vl-stmt-guts
              • Vl-always-convert-regport
              • Vl-always-scary-regs
              • Eliminitial
              • Ifmerge
              • Vl-edge-control-p
              • Elimalways
            • Gatesplit
            • Gate-elim
            • Expression-optimization
            • Elim-supplies
            • Wildelim
            • Drop-blankports
            • Clean-warnings
            • Addinstnames
            • Custom-transform-hooks
            • Annotate
            • Latchcode
            • Elim-unused-vars
            • Problem-modules
          • Lint
          • Mlib
          • Server
          • Kit
          • Printer
          • Esim-vl
          • Well-formedness
        • Sv
        • Fgl
        • Vwsim
        • Vl
        • X86isa
        • Svl
        • Rtl
      • Software-verification
      • Math
      • Testing-utilities
    • Stmtrewrite

    Vl-ifstmt-combine-rewrite

    Eliminate pure-null if statements and merge simply nested ifs.

    Signature
    (vl-ifstmt-combine-rewrite condition truebranch falsebranch atts) 
      → 
    stmt
    Arguments
    condition — Guard (vl-expr-p condition).
    truebranch — Guard (vl-stmt-p truebranch).
    falsebranch — Guard (vl-stmt-p falsebranch).
    atts — Guard (vl-atts-p atts).
    Returns
    stmt — Type (vl-stmt-p stmt), given the guard.

    There are probably other things we could do here. For now, we just carry out two simple rewrites:

    // Rewrite 1:
    
       if (test)      -->    null
          [null]
       else
          [null]
    
    // Rewrite 2:
    
       if (test1)            if (test1 && test2)
         if (test2)   -->       body
           body

    Definitions and Theorems

    Function: vl-ifstmt-combine-rewrite

    (defun vl-ifstmt-combine-rewrite
           (condition truebranch falsebranch atts)
     (declare (xargs :guard (and (vl-expr-p condition)
                                 (vl-stmt-p truebranch)
                                 (vl-stmt-p falsebranch)
                                 (vl-atts-p atts))))
     (let ((__function__ 'vl-ifstmt-combine-rewrite))
       (declare (ignorable __function__))
       (b*
        ((fail-to-apply (make-vl-ifstmt :condition condition
                                        :truebranch truebranch
                                        :falsebranch falsebranch
                                        :atts atts))
         ((when (and (vl-nullstmt-p truebranch)
                     (vl-nullstmt-p falsebranch)))
          (make-vl-nullstmt))
         ((unless (vl-ifstmt-p truebranch))
          fail-to-apply)
         ((unless (vl-nullstmt-p falsebranch))
          fail-to-apply)
         ((vl-ifstmt inner) truebranch)
         ((unless (vl-nullstmt-p inner.falsebranch))
          fail-to-apply)
         (new-condition
              (make-vl-nonatom :op :vl-binary-logand
                               :args (list condition inner.condition))))
        (make-vl-ifstmt :condition new-condition
                        :truebranch inner.truebranch
                        :falsebranch falsebranch
                        :atts (acons "VL_COMBINED_IF" nil atts)))))

    Theorem: vl-stmt-p-of-vl-ifstmt-combine-rewrite

    (defthm vl-stmt-p-of-vl-ifstmt-combine-rewrite
      (implies (and (force (vl-expr-p condition))
                    (force (vl-stmt-p truebranch))
                    (force (vl-stmt-p falsebranch))
                    (force (vl-atts-p atts)))
               (b* ((stmt (vl-ifstmt-combine-rewrite
                               condition truebranch falsebranch atts)))
                 (vl-stmt-p stmt)))
      :rule-classes :rewrite)